/*
检测起始位，即检测到数据输入引脚由高电平变为低电平，输出一个高电平脉冲
Rx_pin_in: 串行输入数据引脚
*/
module detect(clk,rst,Rx_pin_in,h1_sig);
input clk,rst,Rx_pin_in;
output h1_sig;
reg h1_f1;
reg h1_f2;

always @(posedge clk or negedge rst)
begin
    if(!rst)
	 begin
	     h1_f1<=1'b1;
		  h1_f2<=1'b1;
	 end
	 else
	 begin
	     h1_f1<=Rx_pin_in;
		  h1_f2<=h1_f1;
	 end
end

assign h1_sig =h1_f2&(~h1_f1);
endmodule
